1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel package assembly for semiconductor memory devices and application specific integrated circuit (ASIC) wherein a solder-bumped flip chip is packaged on a low cost land-grid array (LGA) chip scale package (CSP). The low-cost package requires no solder-balls on the package substrate. The weight, size, and profile-height of the electronic package are reduced. Better electrical and thermal performance is achieved. Also, the electronic package is produced at a very low cost by employing simplified and high-yielding processes.
2. Description of the Prior Art
Several difficulties still limit the broad applications of a chip scale packaging technology in the electronic-packaging industry despite the fact that chip scale packages (CSP) provide many advantages. These advantages include but not limited to the reduced sizes, weights and more reliable electrical connections achievable with this packaging configuration. Specifically, a major difficulty is related to the issue of CSP production cost The industry is not very successful in providing practical CSP assemblies, which can be manufactured by simple processes at more competitive low costs. Related to the issue is also the manufacture equipment, the materials, the yields of each production-step, and the complexity involved in implementing the manufacturing processes. Due to those reasons, even though there are at least forty different kinds of CSP packages, and even there are continuous efforts to improve the state of the art of electronic packaging, these CSP packages are either too expensive or difficult to attach to a printed circuit board (PCB). A low cost CSP package manufactured by simple processing step to produce highly reliable IC packages is still a goal, which cannot be easily achieved.
The following descriptions are provided for better understanding of the art of electronic packaging technology. One of the difficulties in shrinking the size of an electronic package assembly is due to the area requirements of a substrate to support and contain the IC device. Certain substrate areas are required to spread the metal traces outwardly, i.e., fanning out of the metal traces toward the perimeter of the substrate, in order to form connections to the solder balls or contact pads for external circuit interfaces during next level of integration. The areas required for a substrate applied to fan out the metal traces could become as large as eight to fifteen times the size of the IC chip unless multiple layers are used to reduce the surface areas. The fan out requirement often offsets the space savings achieved by increasing the circuit density with smaller line-widths.
Modern semiconductor packages typically includes a substrate to mount an integrated circuit (IC) chip thereon. The areas on the top surface of the substrate next to the mounted chip are then applied to redistribute or fan out the input and output signals from the IC device. The substrate can be a metal, e.g., copper lead-frame, a laminated epoxy glass, or a ceramic plate. Polymeric encapsulants or plastic molding compounds are used to seal off the device. As the clock speed increases to several hundred megahertz or higher, the speed of signal redistribution impacted by the packaging configurations often becomes a limiting design factor of device performance. Conventional electrical circuit design and packaging technology may no longer be adequate to satisfy the high-speed signal transmission requirements. For high-speed high performance devices, in order to overcome the limitations, there is a demand for improved circuit design and packaging techniques where the signal redistribution processes can be more rapidly and reliably carried out.
A technique to improve the signal redistribution from the semiconductor device is to form a ball-grid array (BGA) assembly package, as that shown in FIG. 1 which shows a cross sectional view for a conventional BGA package assembly 10. The package assembly 10 is formed on a multiple layer substrate 15 which supports a semiconductor device 20 disposed in a center portion of the substrate 15. A plurality of wires 25 for connecting the ground, the power and the signal input and output terminals on the semiconductor device 20 are formed to contact the bonding pads 30 disposed near the semiconductor device 20. The pitch between the bonding pads, i.e., the distance between the bonding pads, is approximately eight to ten mils with a gap of three to six mills between the pads. For each bonding pad 30, a metal trace 35 is formed to spread out toward the outer perimeter of the substrate 15 in order to be compatible with the pitches of the regular connection terminals provided on a printed circuit board (PCB). The connection terminals on the PCB are for next level of integration to an electronic device, e.g., a board for a personal computer. These metal traces 35 are formed to have a fan shape such that the distance between them are gradually increased. On the outer edge of the substrate 15, a plurality of through-holes 40 are formed to connect the metal traces 35 to a plurality of solder balls 45 disposed on the bottom surface of the substrate 15. The pitches between the solder balls are now increased to approximately fifty mils. The solder balls 45 are arranged to have compatible configuration suitable to conveniently connect to contact terminals formed on a printed circuit board to be incorporated into an electronic device.
Applying a technique discussed above, there is an intrinsic area requirement near the semiconductor device 20 in the central portion of the top surface of the substrate 15. This area is required to allow a space for outward extension of the metal traces 35 in fanning out toward the edge of the substrate 15. Therefore, in this type of configuration, the bonding pads 30 are disposed near the semi-conductor device 20. An outward spreading distribution for metal traces 35 are applied to achieve signal "redistribution", in order to transmit the signals to the solder balls 45 via the through holes 40 on the outer edge. Therefore, a substrate 15 must have significantly greater area than the semiconductor device 20.
More recently, a chip scale packaging (CSP) technology is employed to reduce the size of the electronic packages. A CSP package disclosed by Motorola is shown in FIG. 2. The unique feature of the CSP is to use a substrate carrier or interposer to redistribute the very fine pitch of the peripheral pads on the chip, e.g., as small as 0.075 mm, to a much larger pitch, e.g., 1.0 mm, 0.75 mm or 0.5 mm, area array pads on the PCB. In general, the CSP packages have the advantages that they are easier to test and burn-in for the known-good dies. They are also easier to handle, to assemble, to rework, to standardize, to protect the die, to process die-shrink and are subjected to less infrastructure constrains. The Motorola's CSP as shown in FIG. 2 is a slightly larger than IC carrier (SLICC) package. Motorola's SLICC package is designed to provide all the advantages discussed above. However, the SLICC shown in FIG. 2 implements a high temperature 95 wt % Pb-5 wt % Sn or 97 wt % Pb-3 wt % Sn solder bumped chips and solder balled substrate configuration. In order to be surface mount compatible, a layer of 63 wt % Sn/37 wt % Pb solder must be coated on the substrate. It is difficult to reduce the production cost of this package due to its more complicate processing steps involved in processing the high temperature solder-bumps and the solder-balls implemented in the CSP package.
Another CSP package is a LGA package disclosed by Matsushita (Kunitomo, Y. "Practical Chip Size Package Realized by Ceramic LGA Substrate and SBB Technology" Proceeding of SMI Conference, August 1995, pp 18-25). Gold stud bump bonding (SBB) technology with isotropic conductive adhesive is employed to assembly the chip to the ceramic substrate. Such process is quite expensive. Furthermore, the CSP's solder joints on a printed circuit board are not reliable due to large thermal expansion mismatch. The thermal expansion coefficients (TEC) of the ceramic substrate is 6.5.times.10-6 in/.degree. C. and that of the FR-4 PCB is 18.5.times.10-6 in/.degree. C.
Therefore, a need still exits in the art to provide an improved package assembly with novel and simplified processing steps to reduce the production costs of the CSP packages.